1. Technical Field
This invention relates in general to disk storage devices and, more particularly, to a high speed preamplifier/write driver.
2. Description of the Related Art
Almost all business and home computers use a hard disk drive storage system for mass storage requirements. A hard disk drive stores data by individually modifying the magnetic orientation of small regions of a disk surface. As shown in FIG. 1, a hard disk drive 10 typically includes one or more rotating disks 12. A head assembly 14 associated with each surface of the disks 12 typically includes separate read and write heads for reading data from the disk and writing data to the disk. The write head is essentially a small coil of wire which stores data by magnetizing small regions along a disk's tracks. A current driven through the write head in a first direction magnetizes a small region of the disk under the head at a first orientation and a current driven through the write head in the opposite direction magnetizes a, small region of the disk under the head at a second orientation. The read head distinguishes the magnetic orientation of each bit location to derive logical “1s” and “0s”.
The circuit which drives the write head is referred to as a “write driver”, which is part of the read/write preamplifier 16. The write driver controls the direction of the flow of current through the head, responsive to information from the channel circuitry 18. The channel circuitry receives data from the hard drive controller 20 of the computer 22.
A recent requirement from disk drive manufacturers is that the preamplifier write driver provides a symmetric write driver signal for reduced noise coupling. A symmetric write driver must have equal and opposite positive and negative write driver signals over all frequency data patterns. These write driver signals must be symmetric in amplitude as well as transient behavior. If the positive and negative write driver signals are well matched in amplitude and transient behavior, the write driver will have virtually no common-mode signal component. The requirement of a symmetrical write driver is driven by read head reliability as the new generation of magneto-resistive (MR) heads is much more sensitive to capacitive coupling from the write driver. Non-symmetrical write drivers with large common-mode voltage components can capacitively couple damaging voltage levels, both differentially and single-ended, to the read head. Generally symmetrical write drivers have been developed to address this problem.
Write drivers drive the write head differentially to achieve the maximum voltage possible across the write head for both positive and negative transitions. The requirement of driving the write head differentially means that both sides of the write driver must have bidirectional drive capability.
FIG. 2 illustrates an example of a typical prior art write driver 30 using an H-bridge configuration. WDX and WDY are the differential data signals for driving a current through head 32 in a desired direction. If WDX is at a higher potential than WDY, then NPN transistors Q0L and Q2L will conduct, while NPN transistors Q0R and Q2R will not conduct. Q2L will lower the voltage at the base of Q1L through the trans-resistance block (which may be as simple as a resistor), causing Q1L to not conduct. With Q2R not conducting, the base of Q1R will be pulled to near Vcc, causing it to conduct as well. Accordingly, a current path is established from Vcc to Vee (as shown by the dotted line) through Q1R, head 32, Q0L and R1. Additionally, Q2L will lower the voltage at the base of PNP transistor Q3R through block trans-resistance block, causing Q3R to conduct as well. The current through head 32 will equal the sum of the current through Q3R and Q1R.
Similarly, if WDY is at higher potential than WDX, current will flow in through head 32 in the opposite direction as the current path will flow through Q3L and Q1L, head 32, Q0R and R1.
The PNP transistors Q3L and Q3R perform an important function of providing a larger current path through head 32 through improved top-side drive capability. Unfortunately, since most IC processes do not have true complimentary active devices, from a switching speed perspective, write drivers of the type shown in FIG. 2 are unbalanced, due to the PNP transistor being slower than the NPN transistor for most processes (in some processes, the PNP are faster than the NPN). For fast switching, circuit designers design the circuit such that the transistors with the faster technology (usually the NPN) are directly driven by the differential data signals (WDX and WDY). For ease of illustration in the remainder of the specification, it will be assumed that NPN will be the faster of the two device technologies.
The problem with unbalanced write drivers is shown in the graph of FIG. 3. FIG. 3 illustrates the voltage at nodes HWX and HWY as current switches direction through head 32. At steady-state, there is a relatively low voltage across head 32. However, when the direction of current through head 32 switches, Q0L or Q0R will pull one side of the head 32 towards Vee and transistors Q1L or Q1R along with Q3L or Q3R will pull the other side towards Vcc. Using the example where WDX>WDY, Q0L will rapidly pull HWX low, because of the superior speed of the NPN transistor, while the slower speed of PNP transistor Q3R and the RC time constant in series with the data path through Q1R pull HWY high at a slower rate. This design has an inherent asymmetry. As a result, the common mode voltage (the average of the voltages at HWX and HWY) across the head fluctuates rapidly (see FIG. 10), which capacitively couples to the read head and can cause damage to the read head.
Accordingly, a need has arisen for a balance write driver with very low common-mode components.